There are two basic types of memory, volatile memory and nonvolatile memory. Volatile memory (e.g., DRAM, SRAM, etc.) comprises devices that lose any content stored in them when they lose power. Conversely, non-volatile memory (e.g., flash, EEPROM, FeRAM, etc.) comprises devices that retain any content stored in them even when they are not powered.
Typically, a non-volatile memory (NVM) cell is formed using either a charge trapping device or a floating gate MOS device.
In a charge trapping device, a non-conductive charge trapping layer is vertically displaced between a gate and an underlying substrate, comprising a source and a drain. When a potential difference is applied to the gate and the source/drain, an electric field is generated in the device, providing charge carriers (e.g., electrons, holes) to the charge trapping layer. When the electric field is removed, the charge carriers are trapped in the charge trapping layer where they corresponding to a data state (e.g., a “0” or “1”). Alternatively, the charge trapping layer may be horizontally placed between two materials.
FIG. 1 illustrates a schematic diagram 100 of an exemplary non-volatile memory (NVM) cell comprising a floating gate metal-oxide-semiconductor (MOS) device. The floating gate MOS device comprises a transistor having a source/drain 102, a drain/source 104, a control gate 110, and a floating gate 108. The source/drain 102 and drain/source 104 are comprised within the substrate 106 of the semiconductor body. The control gate 110 is located vertically above the source 102 and the drain 104. The floating gate 108 is disposed between the substrate 106 (comprising source 102 and drain 104) and the control gate 110 and is electrically isolated from the substrate 106 and control gate 110 by a dielectric material 112. The dielectric material 112 between the floating gate 108 and the substrate 106 comprises a thin gate oxide layer (e.g., a thin silicon dioxide layer) or a stack of different dielectric layers (e.g. comprising dielectrics with different dielectric constants).
During operation, programming (e.g., writing data to) the NVM cell may be performed by transferring charge carriers (e.g., electrons, holes) from the substrate (e.g., the source and/or the drain) to the floating gate 108 by tunneling through the thin gate oxide layer (e.g., exemplary charge carrier motion illustrated as 114). In particular, a voltage may be applied to the source/drain region 102 of the device and a corresponding voltage may also be applied to the control gate 110. Such biasing providing a potential at the floating gate that is lower in absolute value than the potential of the drain resulting in an electric field that causes ‘hot electrons’ or ‘hot holes’ to be injected, from the source/drain, to the floating gate by tunneling through the thin gate oxide. When the electric field is removed, the electrons become trapped in the electrically isolated floating gate where they correspond to a stored data state (e.g., a “1” or “0”).